Georgia Tech prototypes Z2RAM hybrid to tackle accelerator memory wall

Engineers at the Georgia Institute of Technology have prototyped a hybrid memory architecture based on zero-capacitor RAM (Z2RAM). The project aims to bridge the operational divide between static random-access memory (SRAM) and dynamic random-access memory (DRAM).

Modern machine learning accelerators face a persistent throughput constraint known as the memory wall. While arithmetic execution units have grown faster, data delivery rates remain throttled by physical interconnects. On-chip SRAM supplies the requisite sub-nanosecond access latencies. However, conventional six-transistor SRAM cells consume considerable die area, occupying roughly 0.02 square micrometres per bit on advanced silicon nodes. This physical footprint limits on-die cache capacity, compelling systems to fetch model parameters frequently from off-package high-bandwidth memory.

Every transaction across an interposer or external memory bus incurs marked latency and energy penalties. In large neural network workloads, moving data across packaging boundaries consumes over half of total package power budgets.

Georgia Tech's design addresses this imbalance by integrating Z2RAM cells into a unified on-die hierarchy. Unlike standard DRAM, Z2RAM stores electrostatic charge directly within the body of a single silicon-on-insulator field-effect transistor, bypassing the need for a separate storage capacitor. This configuration shrinks individual cell dimensions close to single-transistor scaling limits, substantially increasing bit density relative to classic SRAM arrays.

Experimental evaluations demonstrate that the hybrid structure approaches SRAM access latencies while quadrupling the storage density achieved by standard cache banks. By maintaining larger blocks of memory adjacent to execution units, the prototype minimises off-chip bus transactions during model training and inference runs. Intermediate activation layers can remain on-die across longer sequence lengths, lowering both bus congestion and thermal dissipation.

Substantial commercialisation hurdles persist before the technology can reach production accelerators. The floating-body mechanism in Z2RAM requires precise voltage biasing to prevent charge drift, particularly under elevated operating temperatures. Furthermore, fabricating zero-capacitor cells within existing gate-all-around foundry lines demands lithography adjustments that chip fabricators have not yet validated at volume.

Will commercial foundries accept the manufacturing complexity of zero-capacitor cells to relieve accelerator memory constraints?